1. Field of the Invention
The present invention relates to a resistance control method for a nonvolatile variable resistive element in a nonvolatile semiconductor memory device that stores information using the nonvolatile variable resistive element, the resistance control method being for collectively performing one of memory operations of a programming process, an erasure process, and the forming process on a plurality of the elements.
2. Description of the Related Art
In recent years, various device structures, such as FeRAMs (ferroelectric RAMs), MRAMs (magnetic RAMs) and OUMs (ovonic unified memories) have been proposed as next-generation nonvolatile random access memories (NVRAMs) which make high speed operation possible and substitute flash memories, and the competition is severe in the development of memories having higher performance, higher reliability, lower cost and process compatibility. However, these memory devices currently have both good and bad points, and we are far away from realizing an ideal “universal memory” having all the good points of SRAMs, DRAMs and flash memories.
In addition to these existing technologies, resistive random access memories (RRAM) using nonvolatile variable resistive elements having an electrical resistance that changes reversibly when a voltage pulse is applied have been proposed. The structure of these nonvolatile variable resistive elements is extremely simple and, as shown in FIG. 1, the nonvolatile variable resistive element 100 has a structure where a lower electrode 106, a variable resistor 104 and an upper electrode 102 are layered in sequence from the bottom, so that the resistive value changes reversibly when electrical stress, for example a voltage pulse, is applied across the upper electrode 102 and the lower electrode 106. A novel nonvolatile memory device that reads out the resistive value during the operation for reversibly changing the resistance (hereinafter referred to as “switching operation”) can thus be implemented.
As for the material for the variable resistor 104, there is research by Shangquing Liu and Alex Ignatiev, among others, from Houston University, US, and U.S. Pat. No. 6,204,139 and Liu, S. Q. et al. “Electric-pulse-induced reversible Resistance change effect in magneto-resistive films”, Applied Physics Letters, 2000, Vol. 76, p. 2749-2751 disclose a method for reversibly changing the electrical resistance by applying a voltage pulse to a Perovskite material, which is known to have colossal magneto-resistance effects. Here, in the element structure shown as an example in U.S. Pat. No. 6,204,139, a crystalline praseodymium calcium manganese oxide Pr1-XCaXMnO3 (PCMO) film, which is a Perovskite oxide, is used as the material for the variable resistor 104.
In addition, it is known from H. Pagnia et al. “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, Phys. Stat. Sol. (a), 1988, vol. 108, p. 11-65 and Japanese Translation of International Patent Publication 2002-537627 that titanium oxide (TiO2) films, nickel oxide (NiO) films, Zinc oxide (ZnO) films and niobium oxide (Nb2O5) films, which are oxides of transition metals, also exhibit reversible change in the resistance. When such transition metal oxides as titanium oxide and nickel oxide are used as variable resistors, a localized region where the resistivity is low (hereinafter referred to as “filament path”) is created or decomposes in the oxide when the temperature rises, due to a current flowing into the nonvolatile variable resistive element, and this is believed to cause the resistance to change. The electrical properties of such filament paths are disclosed in G. Dearnaley et al. “Electrical phenomena in amorphous oxide films”, Rep. Prog. Phys., 1970, Vol. 33, p. 1129-1191.
That is to say, nonvolatile variable resistive elements are initially in an isolated state after manufacture, and in order to convert them to a state in which they can be switched between a high resistance state and a low resistance state using electrical stress, it is necessary to form a filament path within the nonvolatile variable resistive element by applying a voltage, as shown in I. G. Baek et al., “Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses”, IEDM Technical Digest, 2004, p. 587-590. This process for forming a filament path within a nonvolatile variable resistive element is referred to as a forming process.
FIG. 2 shows the relationship between the level of the voltage pulse applied in the forming process and the thickness of the oxide (cobalt oxide) layer during the time required for a filament path to be formed, so that the forming process can be completed (hereinafter referred to as “forming time”), as shown in Y. Tamai et al. “RRAM Technology for Fast and Low-Power Forming/Switching”, International Conference on Solid State Devices and Materials (SSDM), 2008, p. 1166. The higher the level of the applied voltage is and the thinner the oxide layer is, the shorter the forming time tends to be, and in the case where a forming voltage of 3 V is applied, the forming process completes in 1 μs for an oxide layer of 10 nm, while the forming process completes in 100 μs for 50 nm. Meanwhile, it is necessary to apply a voltage of as high as 20 V to oxide layers of 50 nm in order for the forming process to complete in 1 μs, and application of approximately 3 V is necessary for oxide layers of 10 nm.
Here, the forming time is the cumulative time over which a pulse is applied in the case where a voltage pulse is applied a number of times during the forming process.
As shown in FIG. 2, the forming time depends on the film thickness of the metal oxide for the variable resistor, and the nonvolatile variable resistive elements have different thicknesses, and therefore, there is inconsistency in the forming time between the elements. Therefore, a forming process, which is efficient for converting nonvolatile variable resistive elements to a state in which a switching operation is possible needs to be carried out on each individual element by adjusting the voltage.
However, at the stage of fabrication of memories having a practical size using memory cells with nonvolatile variable resistive elements, it takes too much time to carry out a forming process on each memory cell of the memory, and therefore, it is urgent to shorten the forming time, from the point of view of efficiency in mass production. Concretely, in the case where a forming process is carried out on a memory of 128 Mbytes, 1 μs is necessary for the forming process on one memory cell (1 bit) with an applied voltage of 3 V in the case where the oxide film layer is 10 nm according to the value in Y. Tamai et al. “RRAM Technology for Fast and Low-Power Forming/Switching”, International Conference on Solid State Devices and Materials (SSDM), 2008, p. 1166, and therefore, at least 15 minutes are required to carry out the forming process on each memory cell.
Here, though it is possible to increase the efficiency of the forming process so that the total forming time is shorter when a forming process is simultaneously carried out on a number of memory cells, it is necessary to solve the below described problems in order to do so.
FIG. 3 is an equivalent circuit diagram showing a memory cell array using nonvolatile variable resistive elements, and FIG. 4 shows an equivalent circuit of a unit memory cell. One terminal of a nonvolatile variable resistive element having two terminals is connected to the drain terminal of a selection transistor, and the other is connected to a second selection line (bit line; BL). The gate terminal of the selection transistor is connected to a first selection line (word line; WL) and the source terminal is connected to a third selection line (source line; SL).
In the memory cell array in FIG. 3, where the same memory cells as in FIG. 4 are aligned in a matrix, a voltage is applied through the first selection line WL1, so that the selection transistors are converted to an ON state, and a voltage pulse for a forming process is simultaneously applied to the second selection lines BL1 to BL16, so that a forming process is attempted to be carried out simultaneously on a number of nonvolatile variable resistive elements VR11 to VR1g of the memory cells that are connected to the first selection line WL1.
The time for the forming process is inconsistent between the nonvolatile resistive elements, and therefore, the first memory cell completes the forming process first. Here, it is assumed that the forming of the nonvolatile variable resistive element VR12 that is connected to the second selection line BL2 is completed first. The resistance lowers in the memory cell where the forming process is complete, and therefore, the current that flows through the second selection line BL2 increases due to the completion of the forming process on VR12, and the potential of the third selection line SL1 increases. Thus, the voltage required for the forming process stops being supplied to the other memory cells that are connected to the third selection line SL1, of which the potential has increased.
As a result, the forming time prolongs, or the forming process makes no longer progresses.